dejo

@T4V0 Hello, I've been doing a lot of research on this project these days and I've brought the code to a better level, I hope... But I'm not sure if this simulation...

This is VHDL code:
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity Kitchen_Timer is

port (

clk : in std_logic; -- Clock input

reset : in std_logic; -- Reset input

start : in std_logic; -- Start button input

stop : in std_logic; -- Stop button input

adjust_interval_up : in std_logic; -- Button for increasing alarm interval

adjust_interval_down : in std_logic; -- Button for decreasing alarm interval

alarm : out std_logic -- Alarm output

);

end entity Kitchen_Timer;

architecture Behavioral of Kitchen_Timer is

signal count : integer range 0 to 3600000 := 0; -- Adjust range for 1 hour

signal alarming : std_logic := '0';

signal alarm_interval : integer range 600 to 3600000 := 600; -- Adjust range for 1 hour

begin

process (clk, reset)

begin

if reset = '1' then

count <= 0;

alarming <= '0';

alarm_interval <= 600;

elsif rising_edge(clk) then

if start = '1' then

count <= count + 1;

end if;

if stop = '1' or count = alarm_interval then

count <= 0;

end if;

if adjust_interval_up = '1' then

if alarm_interval < 3600000 then

alarm_interval <= alarm_interval + 600; -- Adjust increment for 1 minute

end if;

elsif adjust_interval_down = '1' then

if alarm_interval > 600 then

alarm_interval <= alarm_interval - 600; -- Adjust decrement for 1 minute

end if;

end if;

end if;

end process;

alarming <= '1' when count >= alarm_interval else '0';

alarm <= alarming;

end architecture Behavioral;

This is Testbench:
library ieee;

use ieee.std_logic_1164.all;

entity tb_Kitchen_Timer is

end tb_Kitchen_Timer;

architecture tb of tb_Kitchen_Timer is

component Kitchen_Timer

port (

clk : in std_logic;

reset : in std_logic;

start : in std_logic;

stop : in std_logic;

adjust_interval_up : in std_logic;

adjust_interval_down : in std_logic;

alarm : out std_logic

);

end component;

signal clk : std_logic := '0';

signal reset : std_logic := '0';

signal start : std_logic := '0';

signal stop : std_logic := '0';

signal adjust_interval_up : std_logic := '0';

signal adjust_interval_down : std_logic := '0';

signal alarm : std_logic;

constant TbPeriod : time := 1 us; -- Set the clock period to 1us

signal TbClock : std_logic := '0';

signal TbSimEnded : std_logic := '0';

begin

dut : Kitchen_Timer

port map (

clk => clk,

reset => reset,

start => start,

stop => stop,

adjust_interval_up => adjust_interval_up,

adjust_interval_down => adjust_interval_down,

alarm => alarm

);

-- Clock generation

TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

clk <= TbClock;

stimuli : process

begin

-- Reset generation

reset <= '1';

wait for 20 us; -- Adjust delay to fit the new clock period

reset <= '0';

-- Add your stimuli and test cases here

-- For example:

start <= '1';

wait for 50 us; -- Adjust delay to fit the new clock period

start <= '0';

wait for 400 us; -- Adjust delay to fit the new clock period

adjust_interval_up <= '1';

wait for 20 us; -- Adjust delay to fit the new clock period

adjust_interval_up <= '0';

wait for 50 us; -- Adjust delay to fit the new clock period

adjust_interval_down <= '1';

wait for 20 us; -- Adjust delay to fit the new clock period

adjust_interval_down <= '0';

wait for 50 us; -- Adjust delay to fit the new clock period

-- ...

-- Stop the clock and hence terminate the simulation

TbSimEnded <= '1';

wait;

end process;

end tb;

-- Configuration block below is required by some simulators. Usually no need to edit.

configuration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is

for tb

end for;

end cfg_tb_Kitchen_Timer;
And this is result of simulation:

@T4V0 Thanks for the answer, but I think I didn't understand you very well, can you send me the code with the modifications so that I know what exactly you mean?
Thank you very much, in advance